Resorcerer's PowerPC and Altivec (Velocity Engine) Machine Code to English Disassembler

Mathemaesthetics has developed a PowerPC code disassembler that works analogously to Apple's Disassembler library, except that our library has two extra outputs: the instruction Etymology and the instruction Explanation. Both of these outputs are C strings that are currently in English only.

This library is in turn incorporated into Resorcerer's general purpose Hex Editor, which reconfigures itself as a PowerPC code editor whenever it opens a data structure (resource) of type 'pwpc' (or a synonym type). While editing a stream of instructions, pointing the mouse at any given 4-byte instruction not only disassembles it to Assembler, but also to its Etymology and Explanation. Some sample output is shown in the tables below.

Sample PowerPC Instructions (Resorcerer 2.4 or later)

Input Instruction
Output Assembly
Output Etymology
Output Explanation
cntlzw r0,r0
Count Leading Zeros Word
Place into r0 the number of consecutive bits, counting from the high-order bit down, found in r0.
stmw r27, 0xFFEC(SP)
Store Multiple Word
Store 5 32-bit words from registers r27 through r31 into consecutive words beginning at address SP-0x0014 (or SP-20, both the same as SP+0xFFEC).
tdgti r9,2341
Trap Doubleword Greater Than Immediate [64-bit only]
Invoke the system trap handler if r9 > 2341
fnmadd. fp31,fp31,fp31,fp31
Floating Negative Multiply-Add and Record
Multiply fp31 by fp31, add fp31, place the negative of the result into fp31 and set the result's class and sign bits (15, 16-19) of the floating point status and control register, and record exception summary and overflow conditions in CR1.
bdzl+ *+0x5264
Branch Decrement Zero Link (Taken)
Subtract 1 from the loop counter; if it's 0 jump ahead 5273 instructions after this one, and set the link register to the address of the instruction after this one (mark branch likely to be taken).
rlwimi. r21,r27,12,9,9
Rotate Left Word Immediate then Mask Insert
Rotate contents of r27 left by 12 bits; build mask of 0's with bits 9-9 set to 1 (0x00400000); then set the bits (controlled by mask) in r21 to the corresponding rotated bits, and record <, >, and = conditions in CR0.

Sample Altivec Instructions (Resorcerer 2.4.1 or later)

Input Instruction
Output Assembly
Output Etymology
Output Explanation
dstsst r10,r4,0
Data Stream Touch for Store Transient [Altivec]
Redefine transient data stream 0, soon to be stored at r10 using bits [3-7 (or 32 if all 0); 8-15 (or 256 if all 0); and 16-31 (or +32767 if all 0)] of r4 for the stream's block [size; count; and signed stride], respectively.
vcmpgtuh. v7,v3,v1
Vector Compare if Greater Than Unsigned Halfword and Record [Altivec]
For each of 8 unsigned 16-bit half-word vector elements, set the 16-bit half-word v7[i] to all 1's if v3[i] is greater than v1[i], and all 0's if not (if either element in comparison is a NaN, always all 0's), and set condition register CR6 to 0bx0y0, where x is 1 if all comparisons are true, y is 1 if none are true, and 0 otherwise.
vmhraddshs v1,v2,v3,v4
Vector Multiply High Round and Add Signed Halfword Saturate [Altivec]
For each of 8 signed 16-bit half-word vector elements, set a 32-bit temporary TMP to (v2[i] * v3[i]) + 0x0000_4000, then set v1[i] to the 16-bit saturated sum of the high-order 16 bits of TMP and sign-extended v4[i]; if any saturation occurs, set bit 31 (SAT) of Vector Status Control Register (VSCR) to 1.
vrsqrtefp v27,v1
Vector Reciprocal Square Root Estimate Floating Point [Altivec]
For each of 4 32-bit float vector elements, set v27[i] to an estimate of the reciprocal of the square root of v1[i] with a relative error of no more than 1/4096; (-inf, <0, -0, +0, +inf, NaN) result in (QNaN, QNaN, -inf, +inf, 0, QNaN), respectively.

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